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LM5122ZPWPR Scheda tecnica(PDF) 29 Page - Texas Instruments |
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LM5122ZPWPR Scheda tecnica(HTML) 29 Page - Texas Instruments |
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29 / 51 page ![]() MASTER VCC CSN SYNCIN/RT RES SS UVLO VIN SYNCOUT BST SLOPE COMP FB HO LO SW + VOUT VCC CSN SYNCIN/RT RES SS UVLO VIN BST SLOPE COMP FB HO LO SW VCC SLAVE VSUPPLY CSP CSP OPT OPT VSUPPLY 29 LM5122, LM5122-Q1 www.ti.com SNVS954G – FEBRUARY 2013 – REVISED MAY 2016 Product Folder Links: LM5122 LM5122-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Figure 30. Normalized Output Capacitor RMS Ripple Current To configure for dual phase interleaved operation, one device should be configured as a master and the other device should be configured in slave mode by connecting FB to VCC. Also COMP, UVLO, RES, SS and SYNCOUT on the master side should be connected to COMP, UVLO, RES, SS and SYNCIN on slave side respectively. The compensation network is connected between master FB and the common COMP connection. The output capacitors of the two power stages are connected together at the common output. Figure 31. Dual Phase Interleaved Boost Configuration Shown in Figure 32 is a dual phase timing diagram. The 180° phase shift is realized by connecting SYNCOUT on the master side to the SYNCIN on the slave side. |
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