LM5122ZPWPR datasheet(5/51 Pages) TI1

5 / 51 page

LM5122, LM5122-Q1

www.ti.com

SNVS954G – FEBRUARY 2013 – REVISED MAY 2016

Product Folder Links: LM5122 LM5122-Q1

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Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

SLOPE

Slope compensation is programmed by a single resistor between SLOPE and the AGND.

Soft-start programming pin. An external capacitor and an internal 10-

μA current source set the ramp

rate of the internal error amplifier reference during soft-start.

I/O

Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the

high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET

switch through short, low inductance paths.

SYNCIN/RT

The internal oscillator frequency is programmed by a single resistor between RT and the AGND.

The internal oscillator can be synchronized to an external clock by applying a positive pulse signal

into this SYNCIN pin. The recommended maximum internal oscillator frequency in master

configuration is 2 MHz which leads to 1 MHz maximum switching frequency.

SYNCOUT

Clock output pin. SYNCOUT provides 180º shifted clock output for an interleaved operation.

SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section.

UVLO

Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the

shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below

1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the

HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10-

μA

current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external

UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.

VCC

P/O/I

VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to

controller as possible.

VIN

P/I

Supply voltage input source for the VCC regulator. Connect to input capacitor and source power

supply connection with short, low impedance paths.

N/A

Exposed pad of the package. No internal electrical connections. Should be soldered to the large

ground plane to reduce thermal resistance.

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless

otherwise specified, all voltages are referenced to AGND pin.

(2)

See Application Information when input supply voltage is less than the VCC voltage.

(3)

All output pins are not specified to have an external voltage applied.

6 Specifications

6.1 Absolute Maximum Ratings

(1)

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Input

VIN, CSP, CSN

–0.3

BST to SW, FB, MODE, UVLO, OPT, VCC(2)

–0.3

–5.0

105

BST

–0.3

115

SS, SLOPE, SYNCIN/RT

–0.3

CSP to CSN, PGND

–0.3

0.3

Output(3)

HO to SW

–0.3

BST to SW+0.3

–0.3

VCC+0.3

COMP, RES, SYNCOUT

–0.3

Thermal

Junction temperature

–40

150

ºC

Tstg

Storage temperature

–55

150

°C

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