VT6516 datasheet(22/73 Pages) ETC

22 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-22-

Figure 3-3

Following as the listing and figure 3-6 is the algorithm of initialization procedures for 2 bank free list of

SDRAM.

For 16 Mbit SDRAM as following,

-- Bank0 free link list:

128, 129, 131, 134, 136, 137, 139, 142, 144, 145, 147, 150, 152, 153, 155, 158, 160,...

-- Bank1 free link list:

130, 132, 133, 135, 138, 140, 141, 143, 146, 148, 149, 151, 154, 156, 157, 159, 162, 164, ...

For 64 Mbit SDRAM as following,

-- Bank0 free link list:

128 , 129 , 130 , 134 , 135 , 139 , 140 , 141 , 144 , 145 , 146 , 150 , 151 , 155 , 156 , 157 , 160 , ...

--Bank1 free link list:

131 , 132 , 133 , 136 , 137 , 138 , 142 , 143 , 147 , 148 , 149 , 152 , 153 , 154 , 158 , 159 , 163 , …

Figure 3-6: Algorithm of Initialization of Free Link Lists.

#define SRAM_ADDR_REG0 0x2001

#define SRAM_ADDR_REG1 0x2002

#define SRAM_ADDR_REG2 0x2003

#define SRAM_DATA_REG0 0x2004

#define SRAM_DATA_REG1 0x2005

#define SRAM_DATA_REG2 0x2006

#define SRAM_DATA_REG3 0x2007

#define SRAM_CMD_REG

0x2008

#define SRAM_STATUS_REG 0x2009

#define SRAM_ACCESS_IDLE 0x01

#define NULL_PTR

0x7FFFF

void writeLinkEntry(int entryID, int nextID)

{

reg_byte_write (SRAM_ADDR_REG0, entryID*3 & 0x0FF);

reg_byte_cont_write (((entryID*3) >> 8) & 0x0FF);

reg_byte_cont_write (((entryID*3) >> 16) & 0x0FF);

128/0

129/0

130/1

131/0

132/1

Bank 0

Bank 1

133/1

134/0

135/1

136/0

Link/

Frame

Memory Bank

List 0

List 1

128/0

129/0

131/1

130/0

132/1

Bank 0

Bank 1

133/1

134/0

136/1

135/0

Links/

List

Memory Bank

List 0

List 1

137/1

16MBits SDRAM

64MBits SDRAM

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