VT6516 datasheet(57/73 Pages) ETC

57 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-57-

00H

interrupt status register

bit 0: interrupt indication for read/write PHY command

complete

bit 1: interrupt indication for read/write EEPROM command

complete or error

bit 2: interrupt indication for CPU IO port receiving an

incoming packet

bit 3: interrupt indication for CPU IO port finishing the

transmission of an outgoing packet

To clear an interrupt, write 1 to the corresponding IRQSTS bit.

However, write 0 will not cause any change on that interrupt.

IRQSTS

[3:0] 0

01H-

03H

SRAM address register

The data object addressed is in unit of 32 bits. The maximum

allowable SRAM size is 1MB. For SRAM direct access, the CPU

has to (1) set SRAMADDR & SRAMDATA, (2) issue read/write

command by SRAMCMD, and (3) check command status by

SRAMSTS.

SRAMAD

[18:0

]

04H-

07H

SRAM data register

SRAMDA

[31:0

]

08H

SRAM command register

2’b00 : nop

2’b01 : read

2’b10 : write

To make a direct read to SRAM, write SRAMCMD by 2’b01. To

make a direct write to SRAM, write SRAMCMD by 2’b10.

Read/Write will cause the SRAMSTS = ”busy” immediately. As it is

done, SRAMSTS = “done”. A following read to SRAMSTS will

clear it to “idle”.

SRAMCM

[1:0]

09H

SRAM status register

2’b01 : read/write command done

2’b10 : busy (read/write in progress)

2’b00 : idle

SRAMSTS [1:0] 0

R/O

10H-

13H

SDRAM address register

The data object addressed is in unit of 64 bits. The maximum

allowable SDRAM size is 128MB. For SDRAM direct access, the

CPU has to (1) set SDRAMADDR & SDRAMDATA, (2) issue

read/write command by SDRAMCMD, and (3) check command

status by SDRAMSTS.

SDRAMA

DDR

[23:0

]

14H-

1BH

SDRAM data register

SDRAMD

ATA

[63:0

]

1CH

SDRAM command register

2’b00 : nop

2’b01 : read

2’b10 : write

To make a direct read to SDRAM, write SDRAMCMD by 2’b01. To

make a direct write to SDRAM, write SDRAMCMD by 2’b10.

Read/Write will cause the SDRAMSTS = ”busy” immediately. As it

is done, SDRAMSTS = “done”. A following read to SDRAMSTS

will clear it to “idle”.

SDRAMC

[1:0]

1DH

SDRAM status register

2’b01 : read/write command done

2’b10 : busy (read/write in progress)

2’b00 : idle

SDRAMS

[1:0] 0

R/O

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