VT6516 datasheet(28/73 Pages) ETC

28 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-28-

Table 1-1 Address table structure

bit 36-0

High bits (bit 47-11) of MAC address

bit 53-37

port mask (bit[16]: CPU port + bit[15:0]: Ethernet ports 0~15)

bit 55-54

age count

bit 56

Static flag (0: dynamic entry, 1: static entry that can not be updated)

bit 57

VLAN tag flag Reserved (zero)

bit 63-58

VLAN ID

bit 95-64

Reserved for future

And following is the algorithm for the initial the address entries;

#define SRAM_ADDR_REG0 0x2001

#define SRAM_ADDR_REG1 0x2002

#define SRAM_ADDR_REG2 0x2003

#define SRAM_DATA_REG0 0x2004

#define SRAM_DATA_REG1 0x2005

#define SRAM_DATA_REG2 0x2006

#define SRAM_DATA_REG3 0x2007

#define SRAM_CMD_REG

0x2008

#define SRAM_STATUS_REG 0x2009

#define SRAM_ACCESS_IDLE 0x01

void invalidateForwardEntry(int entryID)

{ // the entryID is starting from maxLinkEntryID with width of 96 bits

reg_byte_write (SRAM_ADDR_REG0, (entryID*3+1) & 0x0FF);

reg_byte_cont_write (((entryID*3+1) >> 8) & 0x0FF);

reg_byte_cont_write (((entryID*3+1) >> 16) & 0x0FF);

reg_byte_cont_write (nextID & 0x0FF); entry bits [32]

reg_byte_cont_write ((nextID >> 8) & 0x0FF);

reg_byte_cont_write ((nextID >> 16) & 0x0FF);

reg_byte_cont_write (0x02); // SRAM-write command

while (reg_byte_read(SRAM_STATUS_REG) != SRAM_ACCESS_IDLE) {}

}

3.1.3 CPU interface

The VT6516 support one ISA-like CPU interface, this CPU interface can cooperate with one simple

microprocessor like 8031 or 8051. The CPU will access the switch control and status register to perform

initialization and configurations. By the CPU interface, the frames of CPU port can be read/written from/into the

buffer. The CPU interface can also be used to access the internal registers. The CPU interface also used to access

the external PHY devices through the PHY control module.

The CPU firmware will perform following tasks,

Read the configuration from switch register or from the EEPROM contains

Initialize the switch followed by the configuration, those task including

* DRAM initialization

* SRAM initialization and link list construction

* Program for each network ports for users manual setting or read the auto-negotiation result

start switch to receive frames and forward frames

decrease the learning address aging count

polling the network port change event and change the switch MAC negotiation mode.

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