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WM8912 Scheda tecnica(PDF) 69 Page - Cirrus Logic

Il numero della parte WM8912
Spiegazioni elettronici  Ultra Low Power DAC with Headphone Driver
PDF  129 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8912 Scheda tecnica(HTML) 69 Page - Cirrus Logic

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Production Data
WM8912
w
PD, Rev 4.1, February 2013
69
DAC OPERATION AT 88.2K / 96K
The WM8912 supports DAC operation at 88.2kHz and 96kHz sample rates. This section details
specific conditions applicable to these operating modes.
For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 45. DAC operation at these sample rates is achieved by setting the SAMPLE_RATE
field to half the required sample rate (eg. select 48kHz for 96kHz mode).
For DAC operation at 88.2kHz or 96kHz sample rates, the DAC_OSR128 register must be set to 0.
ReTune
TM Mobile can not be used during 88.2kHz or 96kHz operation, so EQ_ENA must be set to 0.
The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the
“Signal Timing Requirements” section.
SAMPLE RATE
REGISTER CONFIGURATION
CLOCKING RATIO
88.2kHz
SAMPLE_RATE = 101
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
SYSCLK = 128 x fs
96kHz
SAMPLE_RATE = 101
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
SYSCLK = 128 x fs
Table 45 DAC Operation at 88.2kHz and 96kHz Sample Rates



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