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WM8912 Scheda tecnica(PDF) 17 Page - Cirrus Logic |
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WM8912 Scheda tecnica(HTML) 17 Page - Cirrus Logic |
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17 / 129 page ![]() Production Data WM8912 w PD, Rev 4.1, February 2013 17 CONTROL INTERFACE TIMING Figure 4 Control Interface Timing Test Conditions DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT SCLK Frequency 400 kHz SCLK Low Pulse-Width t1 1300 ns SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDA, SCLK Rise Time t6 300 ns SDA, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed tps 0 5 ns |
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