WM8912 datasheet(39/129 Pages) CIRRUS

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Production Data

WM8912

PD, Rev 4.1, February 2013

SEQUENCE

HEADPHONE ENABLE

LINEOUT ENABLE

Step 1

HPL_ENA = 1

HPR_ENA = 1

LINEOUTL_ENA = 1

LINEOUTR_ENA = 1

Step 2

HPL_ENA_DLY = 1

HPR_ENA_DLY = 1

LINEOUTL_ENA_DLY = 1

LINEOUTR_ENA_DLY = 1

Step 3

DC offset correction

Step 4

HPL_ENA_OUTP = 1

HPR_ENA_OUTP = 1

LINEOUTL_ENA_OUTP = 1

LINEOUTR_ENA_OUTP = 1

Step 5

HPL_RMV_SHORT = 1

HPR_RMV_SHORT = 1

LINEOUTL_RMV_SHORT = 1

LINEOUTR_RMV_SHORT = 1

Table 24 Headphone / Line Output Enable Sequence

SEQUENCE

HEADPHONE DISABLE

LINEOUT DISABLE

Step 1

HPL_RMV_SHORT = 0

HPR_RMV_SHORT = 0

LINEOUTL_RMV_SHORT = 0

LINEOUTR_RMV_SHORT = 0

Step 2

HPL_ENA = 0

HPL_ENA_DLY = 0

HPL_ENA_OUTP = 0

HPR_ENA = 0

HPR_ENA_DLY = 0

HPR_ENA_OUTP = 0

LINEOUTL_ENA = 0

LINEOUTL_ENA_DLY = 0

LINEOUTL_ENA_OUTP = 0

LINEOUTR_ENA = 0

LINEOUTR_ENA_DLY = 0

LINEOUTR_ENA_OUTP = 0

Table 25 Headphone / Line Output Disable Sequence

The register bits relating to pop suppression control are defined in Table 26 below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R90 (5Ah)

Analogue

HP 0

HPL_RMV_SHOR

Removes HPL short

0 = HPL short enabled

1 = HPL short removed

For normal operation, this bit should

be set as the final step of the HPL

Enable sequence.

HPL_ENA_OUTP

Enables HPL output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the DC offset

cancellation has been scheduled.

HPL_ENA_DLY

Enables HPL intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the output signal path

has been configured, and before DC

offset cancellation is scheduled. This

bit should be set with at least 20us

delay after HPL_ENA.

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