AD9957SLASHPCBZ datasheet(29/61 Pages) AD

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Data Sheet

AD9957

Rev. F | Page 29 of 61

RAM

STATE

MACHINE

END ADDRESS

START ADDRESS

ADDRESS STEP RATE

RAM MODE

CLK

BASEBAND DATA CLOCK

DDS CLOCK

UP/DOWN COUNTER

I CHANNEL

Q CHANNEL

RAM

SEGMENT

REGISTERS

U/D

(MSBs)

(LSBs)

NOTES

1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.

SCLK

SDIO

SDO

I/O_RESET

Figure 42. RAM Playback to Baseband Data Path

OVERVIEW OF RAM PLAYBACK MODES

The RAM is operational in any one of four different

playback modes.

•

Ramp-up

•

Bidirectional ramp

•

Continuous bidirectional ramp

•

Continuous recirculate

RAM playback is only functional when the AD9957 is pro-

grammed for either the QDUC or interpolating DAC mode.

The RAM playback mode is selected via the 3-bit RAM play-

back mode word located in each of the RAM segment registers.

Thus, the RAM playback mode is segment dependent. The

RAM playback mode bits are detailed in Table 5.

Table 5. RAM Playback Modes

RAM Playback Mode Bits[2:0]

RAM Playback Mode

001

Ramp-up

010

Bidirectional ramp

011

Continuous bidirectional ramp

100

Continuous recirculate

000, 101, 110, 111

Not Valid

The continuous bidirectional ramp and continuous recirculate

modes are not available when the baseband scaling multipliers

serve as the destination of RAM playback.

RAM Ramp-Up Mode

In ramp-up mode, upon assertion of an I/O update or a state

change on the RT pin, the RAM begins playback operation

using the parameters programmed into the selected RAM seg-

ment register. Data is extracted from RAM over the specified

address range contained in the start address and end address of

the active RAM segment register. The data is delivered at the

appropriate rate and to the destination as specified by the RAM

playback destination bit.

The playback rate is governed by the timer internal to the RAM

state machine and its period (Δt) is determined by the state of the

RAM playback destination bit as detailed in the RAM Playback

Operation section.

The internal state machine begins extracting data from the

RAM at the start address and continues to extract data until it

reaches the end address. Upon reaching this address, the state

machine halts.

A graphic representation of the ramp-up mode appears in

Figure 43. The upper trace shows the progression of the RAM

address from the start address to the end address for the active

RAM segment register. The address value advances by one with

each timeout of the timer internal to the state machine. The circled

numbers indicate specific events, explained as follows:

Event 1—an I/O update or state transition on the RT pin. This

event initializes the state machine to the start address of the active

RAM segment register.

Event 2—the state machine reaches the end address of the active

RAM segment register and halts.

START ADDRESS

RAM

ADDRESS

END ADDRESS

1 PDCLK CYCLE

M DDS CLOCK CYCLES

∆t

I/O_UPDATE OR

RT TRANSITION

Figure 43. Ramp-Up Timing Diagram

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