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TLV9051, TLV9052, TLV9054

www.ti.com

SBOS942F – AUGUST 2018 – REVISED JUNE 2019

Product Folder Links: TLV9051 TLV9052 TLV9054

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Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V (continued)

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VOUT = VS / 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(3)

Full shutdown refers to the dual TLV9052S having both channels A and B disabled (SHDN_A = SHDN_B = V–) and the quad TLV9054S

having all channels A to D disabled (SHDN_A/B = SHDN_C/D = V––). For partial shutdown, only one SHDN pin is exercised; in this

mode, the internal biasing circuitry remains operational and the enable time is shorter.

OUTPUT

Voltage output swing from

rail

Positive rail headroom, VS = 5.5 V

RL = 2 kΩ

RL = 10 kΩ

Negative rail headroom, VS = 5.5 V

RL = 2 kΩ

RL = 10 kΩ

ISC

Short-circuit current

VS = 5 V

±50

Open-loop output

impedance

VS = 5 V, f = 5 MHz

250

POWER SUPPLY

Quiescent current per

amplifier

VS = 5.5 V, IO = 0 mA

330

450

µA

VS = 5.5 V, IO = 0 mA

TA = –40°C to 125°C

475

SHUTDOWN

IQSD

Quiescent current per

amplifier

VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS–

0.35

µA

ZSHDN

Output impedance during

shutdown

VS = 1.8 V to 5.5 V, amplifier disabled

10 || 8

GΩ || pF

VIH

High voltage (amplifier

enabled)

VS = 1.8 V to 5.5 V, amplifier enabled

(V–) +

0.9 V

(V–) + 1.1

VIL

Low voltage (amplifier

disabled)

VS = 1.8 V to 5.5 V, amplifier disabled

(V–) + 0.2

(V–) +

0.7 V

tON

Amplifier enable time (full

shutdown)(2)(3)

VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2

µs

Amplifier enable time (partial

shutdown)(2)(3)

VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2

tOFF

Amplifier disable time(2)

VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2

µs

SHDN pin input bias current

(per pin)

VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V

VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V

160

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