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OrderableDevice Scheda tecnica(PDF) 31 Page - Texas Instruments |
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OrderableDevice Scheda tecnica(HTML) 31 Page - Texas Instruments |
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31 / 76 page ![]() OUT1 IN1 ± IN1 + V ± OUT2 IN2 ± IN2 + V+ VS± GND Ground (GND) plane on another layer Keep input traces short and run the input traces as far away from the supply lines as possible . Place components close to device and to each other to reduce parasitic errors . Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . VIN 1 GND RF RG VIN 2 GND R F RG VS+ GND OUT 1 OUT 2 Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . + VIN 2 VOUT 2 RG RF + VIN 1 VOUT 1 RG RF 31 TLV9051, TLV9052, TLV9054 www.ti.com SBOS942F – AUGUST 2018 – REVISED JUNE 2019 Product Folder Links: TLV9051 TLV9052 TLV9054 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated 11.2 Layout Example Figure 43. Schematic Representation for Figure 44 Figure 44. Layout Example |
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