V54C3128804VAT datasheet(8/43 Pages) MOSEL

8 / 43 page

V54C3128804VAT Rev. 1.4 November 2000

MOSEL VITELIC

V54C3128804VAT

Burst Length and Sequence:

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS

-before-RAS refresh of conventional DRAMs. All of

banks must be precharged before applying any re-

fresh mode. An on-chip address counter increments

the word and the bank addresses and no bank infor-

mation is required for both refresh modes.

The chip enters the Auto Refresh mode, when

RAS and CAS are held low and CKE and WE are

held high at a clock timing. The mode restores word

line after the refresh and no external precharge

command is necessary. A minimum tRC time is re-

quired between two automatic refreshes in a burst

refresh mode. The same rule applies to any access

command after the automatic refresh operation.

The chip has an on-chip timer and the Self Re-

fresh mode is available. It enters the mode when

RAS, CAS, and CKE are low and WE is high at a

clock timing. All of external control signals including

the clock are disabled. Returning CKE to high en-

ables the clock and initiates the refresh exit opera-

tion. After the exit command, at least one tRC delay

is required prior to any access command.

DQM Function

DQM has two functions for data I/O read and

write operations. During reads, when it turns to

“high” at a clock timing, data outputs are disabled

and become high impedance after two clock delay

(DQM Data Disable Latency tDQZ ). It also provides

a data mask function for writes. When DQM is acti-

vated, the write operation at the next clock is prohib-

ited (DQM Write Mask Latency tDQW = zero clocks).

Power Down

In order to reduce standby power consumption, a

power down mode is available. All banks must be

precharged and the necessary Precharge delay

(trp) must occur before the SDRAM can enter the

Power Down mode. Once the Power Down mode is

initiated by holding CKE low, all of the receiver cir-

cuits except CLK and CKE are gated off. The Power

Down mode does not perform any refresh opera-

tions, therefore the device can’t remain in Power

Down mode longer than the Refresh period (tref) of

the device. Exit from this mode is performed by tak-

ing CKE “high”. One clock delay is required for

mode entry and exit.

Auto Precharge

Two

methods

are

available

precharge

SDRAMs. In an automatic precharge mode, the

CAS timing accepts one extra address, CA10, to

determine whether the chip restores or not after the

operation. If CA10 is high when a Read Command

is issued, the Read with Auto-Precharge function

is initiated. The SDRAM automatically enters the

precharge operation one clock before the last data

out for CAS latencies 2, two clocks for CAS laten-

cies 3 and three clocks for CAS latencies 4. If CA10

is high when a Write Command is issued, the Write

with Auto-Precharge function is initiated. The

SDRAM automatically enters the precharge opera-

tion a time delay equal to tWR (Write recovery time)

after the last data in.

Burst

Length

Starting Address

(A2 A1 A0)

Sequential Burst Addressing

(decimal)

Interleave Burst Addressing

(decimal)

xx0

xx1

0, 1

1, 0

0, 1

1, 0

4x00

x01

x10

x11

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

000

001

010

011

100

101

110

111

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