V54C3128804VAT datasheet(1/43 Pages) MOSEL

Il numero della parte	V54C3128804VAT

Spiegazioni elettronici	HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8

PDF	43 Pages

Scroll/Zoom	100%

Produttore elettronici	MOSEL [Mosel Vitelic, Corp]

Homepage	http://www.moselvitelic.com

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MOSEL VITELIC

1

V54C3128804VAT

HIGH PERFORMANCE 143/133/125MHz

3.3 VOLT 16M X 8 SYNCHRONOUS DRAM

4 BANKS X 4Mbit X 8

V54C3128804VAT Rev. 1.4 November 2000

PRELIMINARY

7PC

7

8PC

System Frequency (fCK)

143 MHz

125 MHz

Clock Cycle Time (tCK3)

7 ns

8 ns

Clock Access Time (tAC3) CAS Latency = 3

5.4 ns

6 ns

Clock Access Time (tAC2) CAS Latency = 2

5.4 ns

6 ns

Features

I 4 banks x 4Mbit x 8 organization

I High speed data transfer rates up to 143 MHz

I Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

I Single Pulsed RAS Interface

I Data Mask for Read/Write Control

I Four Banks controlled by BA0 & BA1

I Programmable CAS Latency: 2, 3

I Programmable Wrap Sequence: Sequential or

Interleave

I Programmable Burst Length:

1, 2, 4, 8 and Sequential Type

1, 2, 4, 8 for Interleave Type

I Multiple Burst Read with Single Write Operation

I Automatic and Controlled Precharge Command

I Random Column Address every CLK (1-N Rule)

I Power Down Mode

I Auto Refresh and Self Refresh

I Refresh Interval: 4096 cycles/64 ms

I Available in 54 Pin 400 mil TSOP-II

I LVTTL Interface

I Single +3.3 V ±0.3 V Power Supply

Description

The V54C3128804VAT is a four bank Synchro-

nous DRAM organized as 4 banks x 4Mbit x 8. The

V54C3128804VAT achieves high speed data trans-

fer rates up to 143 MHz by employing a chip archi-

tecture that prefetches multiple bits and then

synchronizes the output data to a system clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of

an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

143 MHz is possible depending on burst length,

CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Power

Temperature

Mark

T

7PC

7

8PC

Std.

L

0

°C to 70°C

•

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