V54C3128804VAT datasheet(6/43 Pages) MOSEL

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V54C3128804VAT Rev. 1.4 November 2000

MOSEL VITELIC

V54C3128804VAT

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The

following power on and initialization sequence

guarantees the device is preconditioned to each

users specific needs. Like a conventional DRAM,

the Synchronous DRAM must be powered up and

initialized in a predefined manner. During power on,

all VCC and VCCQ pins must be built up

simultaneously to the specified voltage when the

input signals are held in the “NOP” state. The power

on voltage must not exceed VCC+0.3V on any of

the input pins or VCC supplies. The CLK signal

must be started at the same time. After power on,

an initial pause of 200

µs is required followed by a

precharge of both banks using the precharge

command. To prevent data contention on the DQ

bus during power on, it is required that the DQM and

CKE pins be held high during the initial pause

period. Once all banks have been precharged, the

Mode Register Set Command must be issued to

initialize the Mode Register. A minimum of eight

Auto Refresh cycles (CBR) are also required.These

may be done before or after programming the Mode

unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-

vided into 4 fields. A Burst Length Field to set the

length of the burst, an Addressing Selection bit to

program the column access sequence in a burst cy-

cle (interleaved or sequential), a CAS Latency Field

to set the access time at clock cycle and a Opera-

tion mode field to differentiate between normal op-

eration (Burst read and burst Write) and a special

Burst Read and Single Write mode. The mode set

operation must be done before any activate com-

mand after the initial power up. Any content of the

mode register can be altered by re-executing the

mode set command. All banks must be in pre-

charged state and CKE must be high at least one

clock before the mode set operation. After the mode

quired. Low signals of RAS, CAS, and WE at the

positive edge of the clock activate the mode set op-

eration. Address input data at this timing defines pa-

rameters to be set as shown in the previous table.

Read and Write Operation

When RAS is low and both CAS and WE are high

at the positive edge of the clock, a RAS cycle starts.

According to address data, a word line of the select-

ed bank is activated and all of sense amplifiers as-

sociated to the wordline are set. A CAS cycle is

triggered by setting RAS high and CAS low at a

clock timing after a necessary delay, tRCD, from the

RAS timing. WE is used to define either a read

(WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access

modes. In a single CAS cycle, serial data read or

write operations are allowed at up to a 125 MHz

data rate. The numbers of serial data bits are the

burst length programmed at the mode set opera-

tion, i.e., one of 1, 2, 4, and 8. Column addresses

are segmented by the burst length and serial data

accesses are done within this boundary. The first

column address to be accessed is supplied at the

CAS timing and the subsequent addresses are gen-

erated automatically by the programmed burst

length and its sequence. For example, in a burst

length of 8 with interleave sequence, if the first ad-

dress is ‘2’, then the rest of the burst sequence is 3,

0, 1, 6, 7, 4, and 5.

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