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V54C3128804VAT Scheda tecnica(PDF) 5 Page - Mosel Vitelic, Corp

Il numero della parte V54C3128804VAT
Spiegazioni elettronici  HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8
PDF  43 Pages
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Produttore elettronici  MOSEL [Mosel Vitelic, Corp]
Homepage  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V54C3128804VAT Scheda tecnica(HTML) 5 Page - Mosel Vitelic, Corp

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V54C3128804VAT Rev. 1.4 November 2000
MOSEL VITELIC
V54C3128804VAT
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1.
V = Valid , x = Don’t Care, L = Low Level, H = High Level
2.
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3.
These are state of bank designated by BS0, BS1 signals.
4.
Power Down Mode can not entry in the burst cycle.
Operation
Device
State
CKE
n-1
CKE
nCS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Row Activate
Idle3
HX
L
L
H
H
X
V
V
V
Read
Active3
H
X
LHLHX
V
L
V
Read w/Autoprecharge
Active3
H
X
LHLHX
V
H
V
Write
Active3
H
X
LHL
L
X
V
L
V
Write with Autoprecharge
Active3
H
X
LHL
L
X
V
H
V
Row Precharge
Any
H
X
L
L
H
L
X
X
L
V
Precharge All
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set
Idle
H
X
LLLLX
V
V
V
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
H
XXX
XX
X
X
LH
H
X
Power Down Entry
Idle
Active5
HL
H
XXX
XX
X
X
LH
H
X
Power Down Exit
Any
(Power
Down)
LH
H
XXX
XX
X
X
LH
HL
Data Write/Output Enable
Active
H
X
XXXX
L
X
X
X
Data Write/Output Disable
Active
H
X
XXXX
H
X
X
X



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