AX6800X datasheet(21/57 Pages) ASIX

21 / 57 page

AX6800x

2/4-Port USB KVM Switch SoC

Table 1-13: High Speed SPI Pin Description

High Speed SPI Interface

Name

Type

Pin No

Pin Description

100

MSS0

O5/T/4m 38

(36)

SPI Master controller Slave Select 0

(14).

MSS0 is a tri-stateable output, which requires an external pull-up resistor.

MSS1

O5/T/4m 23

SPI Master controller Slave Select 1

(15).

MSS1 is a tri-stateable output, which requires an external pull-up resistor.

MSS2

O5/T/4m - (25) 39

(40)

SPI Master controller Slave Select 2

(16).

MSS2 is a tri-stateable output, which requires an external pull-up resistor.

MSCLK O5/T/4m 21

(34)

SPI Master controller CLocK

(14). MSCLK is a tri-stateable output. At Mode 0

or 2, SCLK requires external pull-down resistor; while at Mode 1 or 3, SCLK

requires external pull-up resistor.

MMISO I5

(29)

SPI Master controller Master Input Slave Output line

(14).

MMISO is used to receive serial data.

MMOSI O5/T/4m 35

(32)

SPI Master controller Master Output Slave Input line

(14).

MMOSI is used to transmit serial data and is a tri-stateable output.

SSS

- (38) 36

(60)

SPI Slave controller Slave Select

(17).

SSS is an active low input

SSCLK

- (21) 34

(35)

SPI Slave controller CLocK

(17).

SMISO

O5/T/4m - (34) 29

(53)

SPI Slave controller Master Input Slave Output line

(17).

SMISO is used to transmit serial data and is a tri-stateable output.

SMOSI

- (35) 32

(55)

SPI Slave controller Master Output Slave Input line

(17).

SMOSI is used to receive serial data.

Note 14: To enable these multi-function pins, please set MP0_74_PSEL = 1 in HWCFG offset 0x001 and

SPI_SW_PSEL = 0 in HWCFG offset 0x003.In AX68004 package, MSS0/MSCLK/MMISO/MMOSI

have two pinouts options, and the parenthesis indicates the 2

nd option, enabled by setting MP3_30_PSEL

= 1 in HWCFG offset 0x003 and SPI_SW_PSEL = 1.

Note 15: To enable these multi-function pins, please set MP2_0_PSEL = 1 in HWCFG offset 0x002.

Note 16: To enable these multi-function pins, please set MP1_7_PSEL = 1 in HWCFG offset 0x001. MSS2 have

two pinouts options, and the parenthesis indicates the 2

nd option, enabled by setting BUZZER_PSEL = 1

in HWCFG offset 0x003.

Note 17: To enable these multi-function pins, please set MP3_30_PSEL = 1 and SPI_SW_PSEL = 0. In AX68004

package, SSS/SSCLK/SMISO/SMOSI has two pinouts options, and the parenthesis indicates the 2

option, enabled by setting MP0_74_PSEL = 1 and SPI_SW_PSEL = 1.

AX6800X Scheda tecnica(PDF) 21 Page - ASIX Electronics Corporation

AX6800X Scheda tecnica(HTML) 21 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Scheda tecnica Scarica

Link URL