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AX6800X Scheda tecnica(PDF) 38 Page - ASIX Electronics Corporation |
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AX6800X Scheda tecnica(HTML) 38 Page - ASIX Electronics Corporation |
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38 / 57 page  38 AX6800x 2/4-Port USB KVM Switch SoC Copyright © 2015 ASIX Electronics Corporation. All rights reserved. 3.4 Internal Data Memory and SFR Register Map The figure below shows the Internal Data Memory (256 bytes) and Special Function Register (SFR) map of CPU core. The lower internal memory consists of four register banks with eight registers each; a bit addressable segment with 128 bits (16 bytes) begins at 0x20, and a scratch pad area with 208 bytes. With the indirect addressing mode, range 0x80 to 0xFF of the highest 128 bytes of the internal memory is addressed. With the direct addressing mode, range 0x80 to 0xFF, the SFR memory area is accessed. Figure 3-2: The Internal Memory Map of CPU Table 3-2 below shows the CPU SFR Register Map. Note that all registers in the column with Offset+0 are bit addressable. SFR Offset Offset + 0 Offset + 1 Offset + 2 Offset + 3 Offset + 4 Offset + 5 Offset + 6 Offset + 7 0xF8 EIP 0xF0 B 0xE8 EIE STATUS MXAX TA SPICIR SPIDR 0xE0 ACC MCIR MDR U1CIR U1DR 0xD8 WDCON SDSTSR DCIR DDR PS2CIR PS2DR CRR 0xD0 PSW FCIR FDR FCISR FCDP PCKEN 0xC8 T2CON RLDL RLDH TL2 TH2 0xC0 HCIS HCOIS HCCIR HCDR 0xB8 IP DC3ISR DC3INSR DC3ESMR DC3CIR DC3DR 0xB0 P3 DC2ISR DC2INSR DC2ESMR DC2CIR DC2DR 0xA8 IE DC1ISR DC1INSR DC1ESMR DC1CIR DC1DR 0xA0 P2 DC0ISR DC0INSR DC0ESMR DC0CIR DC0DR 0x98 SCON0 SBUF0 WKUPSR ACON PISSR UDCSR 0x90 P1 EIF WTST DPX0 DPX1 I2CCIR I2CDR 0x88 TCON TMOD TL0 TL1 TH0 TH1 CKCON CSRR 0x80 P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON Bolded: are 1T-80390 CPU core related registers. Italic: AX6800x’s peripheral function’s registers. (M): SFR register available in Local Bus Master Mode. (S): SFR register available in Local Bus Slave Mode. (D): SFR register available in Digital Video Port Mode. Table 3-2: The CPU SFR Register Map |
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