AX6800X datasheet(37/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

3.2 Program Memory Map

The CPU has separated address spaces for program and data memory. The Program Memory, Internal Data

Memory, External Data Memory (xDATA), SFRs areas each has its own address spaces.

As shown in below figure, the CPU core can address up to 128K bytes of linear program space without bank select.

The CPU starts execution of program code at location 0x000000 in LARGE mode, after each reset. The CPU can

be then switched to FLAT mode to support 128K bytes of linear program code space.

Program Protection Bit is used to protect the program code be read by ISP or DoCD. This bit is located at the bit7

in the last byte of first 8K in flash memory (address 0x01FFF, bit7). If this bit is set to ‘0’, it will enable the

program code protection. Only perform the flash Mass Erase can set this bit back to ‘1’ to unprotect the program

code.

Figure 3-1: The Program Memory Map of CPU

3.3 External Data (xDATA) Memory Map

The data memory of CPU core is divided onto 32 Kbytes of External Data (xDATA) Memory and 256 bytes of

Internal Data Memory, plus a 128-bytes of SFR memory area.

The CPU core can address up to 32 Kbytes of External Data (xDATA) memory space without bank select. The

xDATA memory is accessed by MOVX instructions only.

CPU Program Memory Address

0x00000

On-chip 8KB

SRAM

0x02000

0x01FFF

On-chip

128KB

Flash

Memory

The CPU program code residing on on-chip 8K bytes

Program SRAM is copied from the on-chip Flash memory

space (0x00000 ~ 0x01FFF) by Program Loader hardware

before CPU starts running, so-called “Program Code

Mirroring”.

When CPU executes program code in this range, it always

fetches from on-chip Program SRAM and runs at zero wait

state (1T). This part of the code is usually used for BOOT

code with system initialization functions.

The program code residing on on-chip Flash memory

space (0x02000 ~ 0x1FFFF) is fetched with wait

states defined by SFR register, WTST [7:0].

0x1FFFF

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