R5F572TFGDFP datasheet(154/176 Pages) RENESAS

154 / 176 page

R01DS0331EJ0100 Rev.1.00

Page 154 of 176

Feb 08, 2019

RX72T Group

5. Electrical Characteristics

Note 1. Cb is the total capacitance of the bus lines.

Note 2. tPcyc: For SCI11, this is the period of PCLKA, and for SCI1, 5, 6, 8, 9, and 12, this is the period of PCLKB.

Figure 5.54

RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output

Timing

Table 5.37

Simple IIC Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol*1

Min.

Max.*2

Unit

Test Conditions

Simple IIC

(Standard-mode)

SSDA input rise time

tSr

—

1000

Figure 5.54

SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal time

tSP

4 × tPcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

—

400

Simple IIC

(Fast-mode)

SSDA input rise time

tSr

—

300

SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal time

tSP

4 × tPcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

—

400

SDA0, SSDAn

(n = 1, 5, 6, 8, 9, 11, 12)

SCL0, SSCLn

(n = 1, 5, 6, 8, 9, 11, 12)

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions

VIH = 0.7 × VCC, VIL = 0.3 × VCC

VOL = 0.6 V, IOL = 6 mA

VOL = 0.4 V, IOL = 3 mA

Sr*1

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition

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