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R5F572TFGDFP Scheda tecnica(PDF) 151 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 151 Page - Renesas Technology Corp |
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151 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 151 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics Figure 5.51 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2) Figure 5.52 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1) tSU tHF tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output RSPI tDr, tDf tH tDr, tDf tSU tH tLEAD tTD tLAG tSA MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT MSB IN MSB OUT tOH tOD tREL SSLA0 input RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input MISOA output MOSIA input RSPI SSn# input SCKn CKPOL = 0 input SCKn CKPOL = 1 input SMISOn output SMOSIn input Simple SPI (n = 1, 5, 6, 8, 9, 11, 12) |
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