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R5F572TFGDFP Scheda tecnica(PDF) 170 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 170 Page - Renesas Technology Corp |
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170 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 170 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics Note 1. Definition of program/erase cycle: The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more than once before the next erase cycle (overwriting is prohibited). Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to guarantee all characteristics listed in this table. Note 3. This shows the characteristic when the program/erase cycle does not exceed the specified value. Table 5.52 Data Flash Memory Characteristics Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Temperature range for program/erase: Ta = Topr Item Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz Unit Min. Typ. Max. Min. Typ. Max. Program time 4 bytes tDP4 — 0.36 3.8 — 0.16 1.7 ms Erase time 64 bytes tDE64 — 3.1 18 — 1.7 10 Blank check time 4 bytes tDBC4 — — 84 — — 30 μs 64 bytes tDBC64 — — 280 — — 100 2 Kbytes tDBC2K — — 6160 — — 2200 Program/erase cycles*1 NDPEC 100000*2 — — 100000*2 — — Cycles Program suspend latency tDSPD — — 264 — — 120 μs Primary erase suspend latency in suspend priority mode tDSESD1 — — 216 — — 120 Secondary erase suspend latency in suspend priority mode tDSESD2 — — 300 — — 300 Erase suspend latency in erase priority mode tDSEED — — 300 — — 300 Forced stop command tFD — — 32 — — 20 Data retention*3 tDDRP 10 — — 10 — — Year |
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