PIMXRT406LCFP4A datasheet(62/100 Pages) NXP

62 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Electrical characteristics

Figure 37. LPSPI Slave mode timing (CPHA = 0)

Table 54. LPSPI Slave mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

1fSCK

Frequency of operation

fperiph / 2

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be

guaranteed this limit is not exceeded.

2tSCK

SCK period

2 x tperiph

—ns

2 tperiph = 1 / fperiph

3tLead

Enable lead time

—

tperiph

—

4tLag

Enable lag time

—

tperiph

—

5tWSCK

Clock (SCK) high or low time

tSCK / 2 - 5

—

6tSU

Data setup time (inputs)

2.7

—

7tHI

Data hold time (inputs)

3.8

—

8ta

Slave access time

—

tperiph

3 Time to data active from high-impedance state

9tdis

Slave MISO disable time

—

tperiph

4 Hold time to high-impedance state

Data valid (after SCK edge)

—

14.5

—

tHO

Data hold time (outputs)

—

MSB IN

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

SEE

NOTE

see

note

(INPUT)

(CPOL=0)

SCK

(CPOL=1)

PCS

(INPUT)

SOUT

(INPUT)

SIN

(OUTPUT)

LSB IN

BIT 6 . . . 1

NOTE: Not defined

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