PIMXRT406LCFP4A datasheet(65/100 Pages) NXP

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Electrical characteristics

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

4.8.3.2

eMMC4.4/4.41 (dual data rate) AC timing

Figure 40 depicts the timing of eMMC4.4/4.41. Table 57 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

Figure 40. eMMC4.4/4.41 timing

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

tIH

1.5

—

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0

–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0

–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 57. eMMC4.4/4.41 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (eMMC4.4/4.41 DDR)

fPP

052

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

050

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

2.5

7.1

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

1.7

—

SD4

uSDHC Input Hold Time

tIH

1.5

—

Table 56. SD/eMMC4.3 interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

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