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ST25DV16KC-JF8D3 Scheda tecnica(PDF) 7 Page - STMicroelectronics

Il numero della parte ST25DV16KC-JF8D3
Spiegazioni elettronici  Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM, fast transfer mode capability and optimized I2C
PDF  203 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST25DV16KC-JF8D3 Scheda tecnica(HTML) 7 Page - STMicroelectronics

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2
Signal descriptions
2.1
Serial link (SCL, SDA)
2.1.1
Serial clock (SCL)
This input signal is used to strobe all data in and out of the ST25DVxxKC. In applications where this signal is used
by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a
pull-up resistor must be connected from serial clock (SCL) to VCC. See Section 9.2 I2C DC and AC parameters
to know how to calculate the value of this pull-up resistor.
2.1.2
Serial data (SDA)
This bidirectional signal is used to transfer data in or out of the ST25DVxxKC. It is an open drain output that may
be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected
from serial data (SDA) to VCC. (Figure 82. I2C Fast mode (fC = 1 MHz): maximum Rbus value versus bus parasitic
capacitance (Cbus) indicates how the value of the pull-up resistor can be calculated).
2.2
Power control (VCC, LPD, VSS)
2.2.1
Supply voltage (VCC)
This pin can be connected to an external DC supply voltage.
Note:
An internal voltage regulator allows the external voltage applied on VCC to supply the ST25DVxxKC, while
preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the VCC pin.
2.2.2
Low power down (LPD)
This input signal is used to control an internal 1.8 V regulator delivering the ST25DVxxKC internal supply. When
LPD is high, this regulator is shut off and its consumption is reduced below 1 µA.
This regulator has a turn on time in the range of 100 µs to be added to the boot duration, before the device
becomes fully operational. The impedance on LDP pin when set high should not exceed 5 kΩ. The LPD pin is
internally pulled down.
This feature is only available on the 10-ball and 12-pin ST25DVxxKC packages.
2.2.3
Ground (VSS)
VSS is the reference for the VCC and VDCG supply voltages and V_EH analogic output voltage.
ST25DV04KC ST25DV16KC ST25DV64KC
Signal descriptions
DS13519 - Rev 3
page 7/203



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