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DSP56004ROM Scheda tecnica(PDF) 34 Page - Freescale Semiconductor, Inc |
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DSP56004ROM Scheda tecnica(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 82 page  2-10 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing 54 CAS Deassertation Pulse Width (Page Mode Access Only) tCP TC – 5 15 — 10 — 7.3 — ns 55 Row Address Valid to RAS Assertion (Row Address Setup Time) tASR TL – 6 4—2— 0.2 — ns 56 RAS Assertion to ROW Address Not Valid (Row Address Hold Time) tRAH slow fast 3 × T C + TH – 14 2 × T C + TH – 14 56 36 — — 39 24 — — 29.2 16.9 — — ns ns 57 Column Address Valid to CAS Assertion (Column Address Setup Time) tASC TL – 6 4—2— 0.2 — ns 58 CAS Assertion to Column Address Not Valid (Column Address Hold Time) tCAH slow fast 3 × T C + TH – 14 2 × T C + TH – 14 56 36 — — 39 24 — — 29.2 16.9 — — ns ns 59 Last CAS Assertion to Column Address Not Valid (Column Address Hold Time) tCAH slow fast 7 × T C + TH – 14 4 × T C + TH – 14 136 76 — — 100 54 — — 78.6 41.6 — — ns ns 60 RAS Assertion to Column Address Not Valid tAR slow fast 7 × T C + TH – 14 5 × T C + TH – 14 136 96 — — 100 69 — — 78.6 53.9 — — ns ns 61 Column Address Valid to RAS Deassertation tRAL slow fast 3 × T C + TL – 7 2 × T C + TL – 7 63 43 — — 46 30 — — 36.2 23.9 — — ns ns 62 CAS, RAS, RD, or WR Deassertation to WR or RD Assertion tRCH, tRRH slow fast 5 × T C – 11 3 × T C – 11 89 49 — — 65 35 — — 50.7 26.0 — — ns ns 63 CAS or RD Deassertation to Data Not Valid (Data Hold Time) tOFF, tGZ 0 0—0— 0 — ns 64 Random Read or Write Cycle Time (Single Access Only) tRC slow fast 12 × T C 8 × T C 240 160 — — 182 121 — — 148 98.8 — — ns ns Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics Symbol Timing Mode Expression 50 MHz 66 MHz 81 MHz Unit Min Max Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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