IMX8ULPCEC datasheet(24/105 Pages) NXP

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3.3.4 1 MHz Low-Power Oscillator (LPO)

The Internal Reference Clock (1 MHz) module is an internal oscillator that can generate a reference clock of 1 MHz. The LPO clock

is enabled in all modes of operation, including all low power modes.

3.3.5 USB PLL

The USB PLL is embedded in the USB transceiver block. This PLL allows an exact 480 MHz to be generated from a supported

reference clock of 24 MHz. The output of this PLL is primarily used for USB operations on USB-OTG0. The USB PLL clock is also

made available as a clock source for other peripherals on the device.

3.3.6 Fixed Frequency PLL (Fixed-freq PLL)

In addition to the main clock output, this PLL also includes 4 Phase Fractional Dividers (PFDs) that can generate other clock

frequencies. There is one instance of the Fixed-freq PLL (PLL0), which provides clocks for the M33 core, buses, and peripherals

in the real-time domain.

3.3.7 Fractional-N PLL (FracN PLL)

The Fractional-N (Frac-N) PLL can generate an output clock 528 MHz from a supported reference clock. In addition to the main

clock output, this PLL also includes up to four Phase Fractional Dividers (PFDs) that can generate other clock frequencies. This

PLL also supports a tunable clock for audio applications.

3.4 Power Management

The i.MX 8ULP implements multiple options minimizing application power consumption:

• On chip power management including regulators, drivers and switches for flexible power supplies, efficient power

consumption and short wake up time

• Multiple power domains and ultra-low power modes allow flexible power saving

• Voltage and frequency scaling in dynamic operating modes

• Software-controlled clock gating for cores and peripherals

3.4.1 Digital PMC

The digital PMC module allows user software to control power modes and of the chip and to optimize power consumption for the

level of functionality needed. There are two instances of digital PMC on this chip, one for each main power domain.

3.4.2 Analog power management controller (Analog PMC)

The Analog PMC consists of voltage/current references, core logic supply regulators, memory supply regulators, back and forward

biasing regulators, monitors and power switches, etc. There are two Analog PMC subsystems, one associated with the M33 power

domain and the other with the A35 power domain.

Table 5. Analog PMC rise and fall trip point specifications

Rise

Fall

Fuse setting

Min

Typ

Max

Min

Typ

Max

LVD1

0x3

0.805

0.825

0.845

0.78

0.8

0.82

LVD2

0x7

0.908

0.928

0.948

0.88

0.9

0.92

LVD3

0x7

0.98

0.928

0.948

0.88

0.9

0.92

Table continues on the next page...

NXP Semiconductors

System control modules

i.MX 8ULP Applications Processor—Commercial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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