IMX8ULPCEC datasheet(13/105 Pages) NXP

13 / 105 page

Table continued from the previous page...

Module

Domain

Description

Memories and memory controllers

LPUART0-7

APD, RTD

The Low Power Universal Asynchronous Receiver/Transmitter

(LPUART) module provides asynchronous, serial communication

capability with external devices. LPUART supports non-return-to-zero

(NRZ) encoding format and IrDA-compatible infrared (low-speed) SIR

format. The LPUART can continue operating while the processor is

in stop mode if an appropriate peripheral clock is available. This

module is designed for low CPU overhead with DMA offloading of FIFO

LPSPI0-5

APD, RTD

The Low Power Serial Peripheral Interface (LPSPI) module implements

an efficient interface to a SPI bus as a master and/or a slave. The

LPSPI can continue operating while the processor is in stop mode if an

appropriate peripheral clock is available. This module is designed for

low CPU overhead with DMA off-loading of FIFO register accesses.

USB-OTG0-1, USB-XBAR

APD, RTD

The Universal System Bus On-The-Go (USB-OTG) module is a USB

2.0-compliant implementation. The registers and data structures of this

USB controller are based on the Enhanced Host Controller Interface

Specification for Universal Serial Bus(EHCI). This module can act as

a host, a device or an On-The-Go negotiable host/device on the USB

bus.

USBDCD

APD

The USBDCD module works with the USB transceiver to detect

whether the USB device is attached to a Charging Port, either a

Dedicated Charging Port (DCP) or a Charging Downstream Port

(CDP).

USB-PHY

APD

The Universal System Bus Physical Layer (USB-PHY) macrocell

implements USB physical layer connecting to USB host/device

systems at low-speed, full-speed, and high-speed. USB-PHY provides

a standard UTMI interface for connection to the USB-OTG controller.

FlexIO0-1

APD, RTD

The Flexible Input/Output (FlexIO) module is capable of supporting a

wide range of protocols including, but not limited to: UART, I2C, SPI,

I2S, camera interface, display interface, PWM waveform generation,

etc.

Timers

LPTMR0-1

APD, RTD

The Low Power Timer (LPTMR) module is a 16-bit timer which

operates as real-time interrupt or pulse accumulator. This LPTMR

module can remain functional when the chip is in low power modes,

provided the reference clock to this timer is active.

LPTPM0-8

APD, RTD

The Timer/Pulse Width Modulation Module (LPTPM or TPM) is a multi-

channel timer module that supports input capture, output compare,

and the generation of PWM signals.The counter, compare and capture

registers are clocked by an asynchronous clock that can remain

enabled in low power modes.

Table continues on the next page...

NXP Semiconductors

i.MX 8ULP modules list

i.MX 8ULP Applications Processor—Commercial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

13 / 105

IMX8ULPCEC Scheda tecnica(PDF) 13 Page - NXP Semiconductors

IMX8ULPCEC Scheda tecnica(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL