IMX8ULPCEC datasheet(85/105 Pages) NXP

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Table 66. ADC electrical specifications (VREFH=1.68 V and VADINmax≤VDD_PTAmax)1 (continued)

Symbol

Description

Min

Typ2

Max

Unit

Notes

INL

Integral

nonlinearity

—

±1.2

—

LSB

5,6

ENOB

Effective Number of Bits

Single-ended mode

Avg = 1

—

10.3

—

Avg = 2

—

10.6

—

Avg = 16

—

11.3

—

Differential mode

Avg = 1

—

11.2

—

Avg = 2

—

Avg = 16

—

SINAD

Signal to noise

plus distortion

SINAD=6.02 x ENOB + 1.76

EFS

Full-scale error —

-4

—

LSB

EZS

Zero-scale error —

0.05

—

LSB

Iin_ext_leak

External

channel

leakage current

—

500

EIL

Input leakage

error

RAS * Iin

1. Values in this table are based on design simulations.

2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are

for reference only, and are not tested in production.

3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low

as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The

RAS/CAS time constant should be kept to < 1 ns.

4. See Figure 37.

5. 1 LSB = (VREFH - VREFL)/2N, N=12

6. ADC conversion clock at max frequency and using linear histogram.

7. Input data used for test was 1 kHz sine wave.

Table 67. ADC electrical specifications (1V≤VREFH<VDD_ANA18MIN and VADINMAX≤VREFH) 1

Symbol

Description

Min

Typ2

Max

Unit

Notes

VADIN

Input voltage VREFL

—

VREFH

—

CADIN

Input

capacitance

—

4.5

—

RADIN

Input

resistance

—

500

—

Ω

Table continues on the next page...

NXP Semiconductors

Specifications—real-time domain

i.MX 8ULP Applications Processor—Commercial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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