AT43USB355 datasheet(7/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

Architectural

Overview

The AT43USB355 is available in 2 versions. The program memory of the AT43USB355E is an

SRAM that is automatically written from an external serial EEPROM during power-on. The

AT43USB355M has a masked ROM program memory. The two versions are pin, function and

binary compatible.

The peripherals and features of the AT43USB355 microcontroller are similar to those of the

AT90S8515, with the exception of the following modifications:

•

The AT43USB355E has a downloadable SRAM and the AT43USB355M has a masked

ROM for program memory

•

No EEPROM

•

No external data memory accesses

•No UART

•

Idle mode not supported

•

USB Hub with attached function

•

On-chip ADC

The embedded USB hardware of the AT43USB355 is a compound device, consisting of a 3

port hub with a permanently attached function on one port. The hub and attached function are

two independent USB devices, each having its own device addresses and control end-points.

The hub has its dedicated interrupt end-point, while the USB function has 3 additional pro-

grammable end-points with separate FIFOs. Two of the FIFOs are 64 bytes deep and the third

is 8 bytes deep.

The microcontroller always runs from a 12 MHz clock that is generated by the USB hardware.

While the nominal and average period of this clock is 83.3 ns, it may have single cycles that

deviate by ±20.8 ns during a phase adjustment by the SIE's clock/data separator of the USB

hardware.

The microcontroller shares most of the control and status registers of the megaAVR Microcon-

troller Family. The registers for managing the USB operations are mapped into its SRAM

space. The I/O section on page 16 summarizes the available I/O registers. The “AVR Register

Set” on page 37 covers the AVR registers. Please refer to the Atmel AVR manual for more

information.

The fast-access register file concept contains 32 x 8-bit general-purpose working registers

with a single clock cycle access time. This means that during one single clock cycle, one Arith-

metic Logic Unit (ALU) operation is executed. Two operands are output from the register file,

the operation is executed, and the result is stored back in the register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing - enabling efficient address calculations. One of the three address pointers

is also used as the address pointer for look-up tables in program memory. These added func-

tion registers are the 16-bit X-, Y- and Z-registers.

The ALU supports arithmetic and logic operations between registers or between a constant

and a register. Single register operations are also executed in the ALU. Figure 3 on page 6

shows the AT43USB355 AVR Enhanced RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used

on the register file as well. This is enabled by the fact that the register file is assigned the 32

lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were

ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as

the Data Space locations following those of the register file, $20 - $5F.

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