AT43USB355 datasheet(28/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

Timer/Counter Interrupt Flag Register – TIFR

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the

hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is

cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1

Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is

executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at

$0000.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the

data in OCR1A - Output Compare Register 1A. OCF1A is cleared by the hardware when exe-

cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a

logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match

InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Inter-

rupt is executed.

• Bit 5 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the

data in OCR1B - Output Compare Register 1B. OCF1B is cleared by the hardware when exe-

cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a

logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match

InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter-

rupt is executed.

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

• Bit 3 – ICF1: - Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1

value has been transferred to the input capture register - ICR1. ICF1 is cleared by the hard-

ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is

cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1

Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt

is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

• Bit 1 – TOV: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the

hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is

cleared by writing a logic one to the flag. When the SREG I- bit, and TOIE0 (Timer/Counter0

Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is

executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

Bit

210

$38 ($58)

TOV1

OCF1A

OCIFB

–

ICF1

–

TOV0

–

TIFR

Read/Write

R/W

Initial Value

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