AT43USB355 datasheet(52/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

Watchdog Timer Control Register – WDTCR

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT43USB355 and will always read as zero.

•Bit 4 – WDTOE: Watch Dog Turn-Off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be

disabled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the

description of the WDE bit for a watchdog disable procedure.

•Bit 3 – WDE: Watch Dog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero)

the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set

(one). To disable an enabled watchdog timer, the following procedure must be followed:

In the same operation, write a logical one to WDTOE and WDE. A logical one must be

written to WDE even though it is set to one before the disable operation starts.

Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watch Dog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding Time-out

Periods are shown in Table 18.

Note:

The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer

is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer

prescale settings. If the Watchdog Timer is enabled without reset, the watchdog timer may not

start to count from zero. To avoid unintentional MCU reset, the Watchdog Timer should be dis-

abled or reset before changing the Watchdog Timer Prescale Select.

Bit

$21 ($41)

–

WDTOE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

Table 18. Watchdog Timer Prescale Select

WDP2

WDP1

WDP0

Number of WDT Oscillator cycles

Time-out

8K cycles

8.2 ms

16K cycles

16.4 ms

32K cycles

33.8 ms

64K cycles

65.6 ms

128K cycles

0.131 s

256K cycles

0.262 s

512K cycles

0.524 s

1,024K cycles

1.048 s

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