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AT43USB355 Scheda tecnica(PDF) 48 Page - ATMEL Corporation |
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AT43USB355 Scheda tecnica(HTML) 48 Page - ATMEL Corporation |
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48 / 115 page ![]() 48 AT43USB355 2603G–USB–04/06 Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con- trol and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the com- pare event. Since the Output Compare Registers OCR1A and OCR1B are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo- rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. Bit 15 14 13 12 11 10 9 8 $2B ($4B) MSB – ––– – – – OCR1AH $2A ($4A) – – ––– – – LSB OCR1AL 7 6 543 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 000 0 0 0 Bit 15 14131211 10 9 8 $29 ($49) MSB ––– – – – – OCR1BH $28 ($48) – ––– – – – LSB OCR1BL 7 654 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 000 0 0 0 0 |
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