CC1010-RTR1 datasheet(30/152 Pages) TI

30 / 152 page

CC1010

SWRS047

Page 30 of 152

EICON (0xD8) - Extended Interrupt Control

Bit

Name

R/W

Reset value

Description

SMOD1

R/W

Serial Port 1 baud rate doubler enable / disable

0 : Serial Port 1 baud rate is normal

1 : Serial Port 1 baud rate is doubled

Reserved, read as 1

FDIE

R/W

Flash / Debug interrupt enable

0 : Interrupt is disabled

1 : Interrupt is enabled (independent of

IE.EA)

FDIF

R/W

Flash / Debug interrupt flag

FDIF is set by hardware when an 8051-initiated write to

Flash program memory is completed or a

TRAP instruction

is executed.

FDIF may also be set by software. FDIF

must be cleared by software before exiting the ISR.

RTCIF

R/W

Real-time clock interrupt flag

RTCIF is set by hardware when an interrupt request is

generated from the real-time clock.

RTCIF may also be set

by software.

RTCIF must be cleared by software before

exiting the ISR.

Reserved, read as 0

EXIF (0x91) - Extended Interrupt Flag

Bit

Name

R/W

Reset value

Description

TF3

R/W

Timer 3 interrupt flag.

TF3 is set by hardware when an interrupt request is

generated from Timer 3.

TF3 may also be set by software.

TF3 must be cleared by software before exiting the ISR.

ADIF

R/W

ADC / DES Interrupt flag.

ADIF is set by hardware when an interrupt request is

generated from the ADC block (

ADCON2.ADCIF) or by the

DES Encryption / Decryption block (

CRPCON.CRPIF).

These interrupts must also be enabled by setting

ADCON2.ADCIE and CRPCON.CRPIE. ADIF may also

be set by software.

ADIF must be cleared by software

before exiting the ISR

TF2

R/W

Timer 2 interrupt flag.

TF2 is set by hardware when an interrupt request is

generated from Timer 2.

TF2 may also be set by software.

TF2 must be cleared by software before exiting the ISR

RFIF

R/W

RF Transmit / receive interrupt flag.

RFIF is set by hardware when an interrupt request is

generated from the RF transceiver block.

RFIF may also

be set by software.

RFIF must be cleared by software

before exiting the ISR.

Reserved, read as 1

Reserved, read as 0

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