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CC1010-RTR1 Scheda tecnica(PDF) 82 Page - Texas Instruments |
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CC1010-RTR1 Scheda tecnica(HTML) 82 Page - Texas Instruments |
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82 / 152 page  CC1010 SWRS047 Page 82 of 152 ADCON 2(0x96) - ADC Control Register 2 Bit Name R/W Reset value Description 7 ADCIE R/W 0 ADC interrupt enable flag. In order for ADCIF to raise an interrupt, EIE.ADIE must also be set. 6 ADCIF R/W 0 ADC interrupt flag. ADCIF must be cleared by software. Because the ADC shares an interrupt line with the DES module, EXIF.ADIF must also be cleared by software before exiting the interrupt service routine. EXIF.ADIF should be cleared first so that the 8051 is ready to receive a new interrupt immediately after ADCIF is cleared. 5:0 ADCDIV R/W 0x00 ADC clock divider. Selects ADC clock divider in steps of 16. 000000: Divider is 16 000001: Divider is 32 … 111111: Divider is 1024 ADTRH (0x97) - ADC Threshold Register Bit Name R/W Reset value Description 7:0 ADTRH(7:0) R/W 0x00 ADC comparator threshold value, used to generate ADC interrupt or chip reset when the threshold is exceeded. |
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