CC1010-RTR1 datasheet(44/152 Pages) TI

44 / 152 page

CC1010

SWRS047

Page 44 of 152

FLTIM=0x05;

/* Set Flash timing for 3.6864 MHz clock frequency */

FLADR=0x01;

/* Write data to the second page in Flash */

EICON|=0x20;

/* Enable Flash interrupt */

IE&= ~0x80;

/* Disable other interrupts */

FLCON=0x10 | (0x100 >> 7);

/* Enable Flash writing, RAM buffer from addr. 0x100 */

PCON|=0x01;

/* Enter Idle Mode to start Flash writing.

15.14 Flash Power Control

The Flash module can be set into different

power modes using the control bits

FLCON.FLASH_LP(1:0) introduced in

the previous section.

After reset, the Flash module is always

active,

drawing

static

current

approximately

2.5

(at

nominal

operating conditions). However, to save

power the Flash module can be set in a

power-down mode between instructions in

Active mode, and always in Idle or Power-

Down mode. This will save approximately

1.5 mA of the Flash current consumption

during operation in Active mode, and 2.5

mA during Idle or Power-Down mode.

15.15 In Circuit Debugging

In order to facilitate a software monitor for

in-circuit debugging/emulation capabilities

a number of hardware support features

have been implemented:

A breakpoint instruction has been added

the

8051's

instruction

set.

The

instruction, given the mnemonic TRAP, is a

single byte instruction with the opcode

0xA5. In the original 8051 the 0xA5

opcode is executed as a NOP instruction

(opcode 0x00.) In the modified core this

instruction raises a highest-level interrupt

(Flash

Debug)

setting

the

corresponding interrupt flag EICON.FDIF

and waiting a sufficient number of

instruction cycles to allow the interrupt to

take effect before the next instruction.

The TRAP instruction can thus be written

over the first byte (opcode) of any other

instruction, the execution of which then will

result in a branch to a software debugging

monitor in the highest priority interrupt

service routine.

Single-stepping through instructions is

supported since exactly one instruction is

executed if an interrupt condition exists

when returning from an interrupt service

routine. Thus, single-stepping can be

accomplished simply by not clearing the

corresponding interrupt flag in the interrupt

service

routine

associated

with

the

software monitor.

A second serial port has been added to

enable debugging communication with a

host PC without disrupting applications

that use the main serial port for other

purposes.

Setting breakpoints and executing the

instructions which have a breakpoint

attached involves writing new data to the

Flash instruction memory several times.

Since the Flash memory can only

withstand 20000 (typical) erase/write-

cycles a simple instruction replacement

mechanism has been implemented. This

feature allows the surveillance of an

address in the instruction memory space

as defined in registers RADRL and RADRH.

When this address is encountered on the

Flash program memory address bus, the

data returned on the data bus is replaced

by the contents of register RDATA. Setting

RADRH=RADRL=0

disables

the

replacement mechanism.

This instruction replacement mechanism

can be used in different ways:

•

A simple way of setting a single soft

(not stored in FLASH) breakpoint, by

setting RDATA to 0xA5 (the TRAP

instruction)

and

RADR

the

breakpoint address.

•

A simple way of restoring the original

opcode byte of an instruction which

has been subjected to a hard (stored

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