USB97C100QFP datasheet(43/64 Pages) SMSC

43 / 64 page

SMSC DS – USB97C100

Page 43

Rev. 01/03/2001

STAT_B

(0x7F61 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER B

BIT

NAME

R/W

DESCRIPTION

EP4TX_EMPTY

Endpoint 4 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP4TX_FULL

Table 72 - Transmit FIFO Status Register C

TXSTAT_C

(0x7F62 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER C

BIT

NAME

R/W

DESCRIPTION

EP11TX_EMPTY

Endpoint 11 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP11TX_FULL

EP10TX_EMPTY

Endpoint 10 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP10TX_FULL

EP9TX_EMPTY

Endpoint 9 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP9TX_FULL

EP8TX_EMPTY

Endpoint 8 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP8TX_FULL

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