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TMD3721 Scheda tecnica(PDF) 39 Page - OSRAM GmbH |
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TMD3721 Scheda tecnica(HTML) 39 Page - OSRAM GmbH |
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39 / 89 page ![]() Page 38 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Register O ver view AGAIN_3_2 Register (Address 0x96) Figure 49: AGAIN_3_2 Register LDR0_CFG Register (Address 0x9A) Figure 50: LDR0_CFG Register Addr: 0x96 AGAIN_3_2 Bit Bit Name Default Access Bit Description 7:4 AGAIN3 1100 RW This field sets the gain of ALS channel 3. See AGAIN1 for the detailed settings. 3:0 AGAIN2 1100 RW This field sets the gain of ALS channel 2. See AGAIN1 for the detailed settings. Addr: 0x9A LDR0_CFG Bit Bit Name Default Access Bit Description 7 Reserved 0 RW Reserved. Must be set to default value. 6EN_LDR_0 1 RW Enables the LDR0. 5:4 ISINK_LSB 01 RW This field sets VCSEL drive current resolution Value VCSEL Drive Current Resolution 00 0.5mA 01 1.0mA 10 1.5mA 11 2.0mA 3:0 PLDRIVE0 0010 RW This field sets the drive current of the VCSEL driver 0. The formula is shown below: Drive Current 0=(PLDRIVE0+1) x ISINK_LSB. The drive current should be configured within the range of 7mA ~12mA. The values are the nominal current. The actual current through the VCSEL is factory trimmed to normalize the IR intensity. |
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