| Motore di ricerca datesheet componenti elettronici |
|
TMD3721 Scheda tecnica(PDF) 49 Page - OSRAM GmbH |
|
|
|||||||||||||||||||||||||||||
TMD3721 Scheda tecnica(HTML) 49 Page - OSRAM GmbH |
|
49 / 89 page ![]() Page 48 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Register O ver view VSYNC_CFG Register (Address 0xB1) Figure 63: VSYNC_CFG Register Addr: 0xB1 VSYNC_CFG Bit Bit Name Default Access Bit Description 7:6 Reserved 00 RW Reserved. Must be set to default value. 5:4 VSYNC_CHG_DET_STP 00 RW VSYNC period change detection step. Once VSYNC period changes from previous cycle by step of period mentioned in the following table, VSYNC_CHG_INT interrupt is generated if VSIEN=1. VSYNC_PRD ={VSYNC_PRD_H, VSYNC_PRD_L} Value Timing 0Compare with VSYNC_PRD[15:10] 1Compare with VSYNC_PRD[15:9] 2Compare with VSYNC_PRD[15:11] 3Compare with VSYNC_PRD[15:12] 3INT_VSYNC_EN 0 RW Enables internal VSYNC. It will be cleared automatically when VSYNC signal is detected on the device VSYNC pin. 2 VSYNC_INVERT 0 RW This bit inverts VSYNC input. 0 – Not inverted; 1 – Inverted; 1:0 VSYNC_WD_TH 0 RW VSYNC watch dog time out. The expiration generates VSYNC_LOST_INT interrupt if VSIEN=1. Value Timing 088.92ms 111.12ms 222.23ms 344.46ms |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |