TMD3721 datasheet(40/89 Pages) OSRAM

40 / 89 page

Datasheet, Public

Page 39

[v3-00] 2023-May-26

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TMD3721 − Register Overview

EYE_SAFETY_CFG Register (Address 0x9E)

Figure 51:

EYE_SAFETY_CFG Register

EYE_SAFETY_STATUS Register (Address 0x9F)

Figure 52:

EYE_SAFETY_STATUS Register

Addr: 0x9E

EYE_SAFETY_CFG

Bit

Bit Name

Default

Access

Bit Description

EYE_SAFETY_CHKS_

ENAB

0RW

Enables VDD and VSS short check for PLDRIVE0, and

also the analog watch dog timer.

Eye safety runs only once at the beginning when

PON and PEN are enabled.

DISABLE_PROX_ON_

WD_FAIL

1RW

Disable the high side switch when the eye safety

watch dog expires.

5:0

Reserved

Reserved. Must be set to default value.

Addr: 0x9F

EYE_SAFETY_STATUS

Bit

Bit Name

Default

Access

Bit Description

7:5

Reserved

Reserved. Must be set to default value.

EYE_SAFETY_WD_

STATUS_SYNCED

When the flag is set, it indicates that the watchdog

has triggered.

When DISABLE_PROX_ON_WD_FAIL is set, the

PLDRIVER0 is disabled when this flag is set.

3:2

Reserved

Reserved. Must be set to default value.

PLDRIVE0_PAD_

SHORT_VSS_FAIL

When the flag is set, it indicates that the VSS check

during eye safety check failed for PLDRIVER0. The

PLDRIVER0 is disabled (no pulses are sent) in case of

failure but the proximity timing is maintained.

When ESIEN is 1, an interrupt is generated in the final

state after PROX_DATA_AVG is complete.

The flag is cleared when PON is made 0. Writing a 1

to this field will clear the flag. To enable clear-by-read

function, INT_READ_CLEAR in the register CFG3 must

be set to 1.

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