MCP3202_06 datasheet(15/28 Pages) MICROCHIP

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DS21034D-page 15

MCP3202

6.0

APPLICATIONS INFORMATION

6.1

Using the MCP3202 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the ris-

ing edge. Depending on how communication routines

are used, it is very possible that the number of clocks

required for communication will not be a multiple of

eight. Therefore, it may be necessary for the MCU to

send more clocks than are actually required. This is

usually done by sending ‘leading zeros’ before the start

bit, which are ignored by the device. As an example,

Figure 6-1 and Figure 6-2 show how the MCP3202 can

be interfaced to a MCU with a hardware SPI port.

Figure 6-1 depicts the operation shown in SPI Mode

0,0, which requires that the SCLK from the MCU idles

in the ‘low’ state, while Figure 6-2 shows the similar

case of SPI Mode 1,1 where the clock idles in the ‘high’

state.

As shown in Figure 6-1, the first byte transmitted to the

A/D Converter contains seven leading zeros before the

start bit. Arranging the leading zeros this way produces

the output 12 bits to fall in positions easily manipulated

by the MCU. The MSB is clocked out of the A/D Con-

verter on the falling edge of clock number 12. After the

second eight clocks have been sent to the device, the

MCU receive buffer will contain three unknown bits (the

output is at high impedance until the null bit is clocked

out), the null bit and the highest order four bits of the

conversion. After the third byte has been sent to the

device, the receive register will contain the lowest order

eight bits of the conversion results. Easier manipulation

of the converted data can be obtained by using this

method.

FIGURE 6-1:

SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2:

SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

1213

1415

SCLK

X = Don’t Care Bits

OUT

NULL

BIT

B11

B10

HI-Z

MCU latches data from A/D Converter

Data is clocked out of

A/D Converter on falling edges

on rising edges of SCLK

Don’t Care

Start

B11

B10

Start

Bit

(Null)

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

MSBF

SGL/

DIFF

SGL/

DIFF

ODD/

SIGN

Data stored into MCU receive

first 8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

last 8 bits

SCLK

X = Don’t Care Bits

OUT

Don’t Care

NULL

BIT

B11

B10

HI-Z

B11

B10

XXXXX

XXX

MCU latches data from A/D Converter

on rising edges of SCLK

Data is clocked out of

A/D Converter on falling edges

Start

Bit

(Null)

Start

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

SGL/

DIFF

ODD/

SIGN

MSBF

Data stored into MCU receive

first 8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

last 8 bits

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