SPSB100 datasheet(66/213 Pages) STMICROELECTRONICS

66 / 213 page

Description

Safety state

SR3

While the MCU is in RUN mode the PMIC shall

monitor the MCU communication and force a

reset of the MCU in case of error.

NRESET and NFSO pins are asserted, output regulators are set back

to their state resulting from a power-up sequence, then NRESET

assertion is maintained for a few ms then released. SPSB100 is in

RECOVERY-1 state. If the MCU communication fault persists then

SPSB100 executes a power-down/power-up sequence. If the MCU

communication fault persists further then output regulators are

stopped, NRESET and NFSO pins are asserted and SPSB100

reaches DEEP-SLEEP state.

SR4

The PMIC shall monitor the local temperature

of each supply regulator and force a shut-down

of the supply regulators in case of temperature

runaway.

Output regulators are stopped, NRESET and NFSO pins are asserted.

SPSB100 waits that the regulator temperature decrease then tries to

power-up again, if the fault is confirmed for 3 successive power-up

then output regulators are stopped, NRESET and NFSO pins are

asserted and SPSB100 reaches DEEP-SLEEP state.

SR5

The PMIC shall monitor the power dissipation

of BOOST external transistors and avoid their

destruction in case of runaway.

BOOST is stopped, error is signaled to MCU, SPSB100 state is

unchanged.

Note:

More details about functional safety can be found in the device safety manual, provided only upon customers

request.

6.1.2

MCU in Smart-Power mode

The following figure shows MCU in Smart-Power mode.

Figure 39. PMIC + MCU in Smart-Power mode

SPSB100

Functional safety concept

DS14640 - Rev 2

page 66/213

SPSB100 Scheda tecnica(PDF) 66 Page - STMicroelectronics