 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
SPSB100 Scheda tecnica(PDF) 163 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPSB100 Scheda tecnica(HTML) 163 Page - STMicroelectronics |
|
|
163 / 213 page  9.7 Status registers Table 209. DSR1 (0x21) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) - (R0) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) RES RES FORCED_SLEEP_WDFAIL BUCK3_OC BUCK3_OV BUCK3_UV BUCK3_PG_TIMEOUT BUCK2_OC Reserved Reserved Device enters in DEEP- SLEEP state after 15 WD fail bit BUCK3 overcurrent bit BUCK3 overvoltage bit BUCK3 undervoltage bit BUCK3 power-good timeout bit BUCK2 overcurrent bit Table 210. DSR1 (0x21) MSB description Bit Name Description 23 RES Reserved 22 RES Reserved 21 FORCED_SLEEP_WDFAIL 1: state machine reaches DEEP-SLEEP after 15 watchdog fails 0: No transition to DEEP-SLEEP due to 15 consecutive watchdog fails 20 BUCK3_OC 1: BUCK3 overcurrent detected 0: No error 19 BUCK3_OV 1: BUCK3 overvoltage detected 0: No error 18 BUCK3_UV 1: BUCK3 undervoltage detected 0: No error 17 BUCK3_PG_TIMEOUT BUCK3 power-good time out during power-up sequence 1: Indicates that the power-good is not reached at the end of timeout Bit is latched until a “read and clear” command 16 BUCK2_OC 1: BUCK2 overcurrent detected 0: No error Table 211. DSR1 (0x21) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) BUCK2_OV BUCK2_UV BUCK2_PG_TIMEOUT BUCK1_OC BUCK1_OV BUCK1_UV BUCK1_PG_TIMEOUT LDO2_PG_TIMEOUT BUCK2 overvoltage bit BUCK2 undervoltage bit BUCK2 power-good timeout bit BUCK1 overcurrent bit BUCK1 overvoltage bit BUCK1 undervoltage bit BUCK1 power-good timeout bit LDO2 power-good timeout bit Table 212. DSR1 (0x21) description Bit Name Description 15 BUCK2_OV 1: BUCK2 overvoltage detected 0: No error 14 BUCK2_UV 1: BUCK2 undervoltage detected 0: No error 13 BUCK2_PG_TIMEOUT BUCK2 power-good time out during power-up sequence 1: Indicates that the power-good is not reached at the end of timeout Bit is latched until a “read and clear” command 12 BUCK1_OC 1: BUCK1 overcurrent detected SPSB100 SPI registers DS14640 - Rev 2 page 163/213 |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
