SPSB100 datasheet(169/213 Pages) STMICROELECTRONICS

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Table 230. DSR4 (0x24) description

Bit

Name

Description

15 SPI_STATUS_WRT 1: SPI writes access to status register

SPI_LBISTED

1: SPI access while SPI is under LBIST test

FBB_OV_EW

FBB over voltage early warning

1: Indicates the voltage at FBB increased above the FBB over voltage early warning threshold

(configured in CR3)

In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ.

Bit is latched until a “read and clear” command

FBB_UV_EW

FBB under voltage early warning

1: Indicates the voltage at FBB decreased below the FBB under voltage early warning threshold

(configured in CR3)

In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ

Bit is latched until a “read and clear” command

VS_UV_EW

VS early warning

1: Indicates the voltage at VS decreased below the VS early warning threshold (configured in CR3)

In ACTIVE and REC-1 modes, an interrupt pulse is generated at IRQ. Bit is latched until a “read and

clear” command

RES

Reserved

TW_CL4

Thermal warning of cluster x

1: Indicates cluster x has reached the thermal warning threshold (TSW)

Bit is latched until a “read and clear” command

TW_CL3

Table 231. DSR4 (0x24) LSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (RC1L)

0 (R)

0 (RC1L)

TW_CL2

TW_CL1

TW_CL0

CRC3

CRC2

CRC1

CRC0

Thermal

warning of

cluster 2 bit

Thermal

warning of

cluster 1 bit

Central

thermal

warning bit

Thermal

warning bit

Cyclic

redundancy

checking bit 3

Cyclic

redundancy

checking bit 2

Cyclic

redundancy

checking bit 1

Cyclic

redundancy

checking bit 0

Table 232. DSR4 (0x24) LSB description

Bit

Name

Description

TW_CL2

TW_CL1

TW_CL0 Central thermal warning

Thermal warning

1: Indicates the temperature has reached the thermal warning threshold (logical OR combination of bits

TW_CLx in DSR6)

CRC 3

CRC 2

CRC 1

CRC 0

SPSB100

SPI registers

DS14640 - Rev 2

page 169/213

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