DAC39RFS10 datasheet(4/175 Pages) TI2

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Table 5-1. Pin Functions

TYPE

DESCRIPTION

NAME

NO.

DAC Outputs

DACOUTA-

A13

DAC channel A analog output negative terminal. Output voltage must comply with DAC

compliance voltage to maintain specified performance.

DACOUTA+

A12

DAC channel A analog output positive terminal. Output voltage must comply with DAC

compliance voltage to maintain specified performance.

DACOUTB-

T13

DAC channel B analog output negative terminal. Output voltage must comply with DAC

compliance voltage to maintain specified performance. Not available in single channel

devices.

DACOUTB+

T12

DAC channel B analog output positive terminal. Output voltage must comply with DAC

compliance voltage to maintain specified performance. Not available in single channel

devices.

Differential Clock and SYSREF Inputs

CLK-

E16

Device clock input negative terminal. There is an internal 100Ω differential termination

between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock

source.

CLK+

D16

Device clock input positive terminal. There is an internal 100Ω differential termination

between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock

source.

SYSREF-

N16

Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω

differential termination between SYSREF+ and SYSREF–.

SYSREF+

M16

Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω

differential termination between SYSREF+ and SYSREF–.

SerDes Interface

6SRX-

Serdes Lane 6 negative input. Includes in package AC-coupling series capacitor and 100Ω

internal termination to 6SRX+.

6SRX+

Serdes Lane 6 positive input. Includes in package AC-coupling series capacitor and 100Ω

internal termination to 6SRX-.

14SRX-

Serdes Lane 14 negative input. Includes in package AC-coupling series capacitor and 100Ω

internal termination to 14SRX+.

14SRX+

Serdes Lane 14 positive input. Includes in package AC-coupling series capacitor and 100Ω

internal termination to 14SRX-.

GPIO Functions

ALARM

ALARM pin is asserted when an internal unmasked alarm is detected. Alarm mask is set by

ALM_MASK register.

FRCLK

Fast reconfiguration interface clock.

FRCS

Fast reconfiguration interface chip select. Internal pullup.

FRDI0

Fast reconfiguration interface data bit 0.

FRDI1

Fast reconfiguration interface data bit 1.

FRDI2

Fast reconfiguration interface data bit 2.

FRDI3

Fast reconfiguration interface data bit 3.

RESET

Device reset input, active low. Must be toggled after power up. Internal pullup.

SCANEN

TI use only, can be left unconnected. Internal pulldown.

SCLK

Serial programming interface (SPI) clock input.

SCS

Serial programming interface (SPI) device select input, active low. Internal pullup.

SDI

Serial programming interface (SPI) data input.

SDO

Serial programming interface (SPI) data output. High impedance when not reading out SPI

data.

SYNC

JESD204C SYNC output, active low.

DDS39RF10, DDS39RFS10

SBASB20 – SEPTEMBER 2024

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