DAC39RFS10 datasheet(98/175 Pages) TI2

98 / 175 page

Note

Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-91. LANE_ARR[15:0] Register

RESERVED

LANE_ARR[n]

R-00b

Table 7-63. LANE_ARR[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

5-0

LANE_ARR[n]

Returns the arrival time of lane n with respect to the internal LMFC/

LEMC that is established by SYSREF. The value returned can be

between 0 and 63 (inclusive), regardless of the multiframe/EMB

length. These registers are valid only when LANE_ARR_RDY =1.

See Programming RBD.

Note: The lane arrival data is captured when attempting to release

the elastic buffer and LANE_ARR_RDY=0. All values are from the

same release attempt.

Note: It may be necessary to use JESD_RST when starting the link

to get accurate lane arrival values.

7.5.3.31 LANE_STATUS[15:0] Register (Offset = 0150h) [Read only, reset = NA]

LANE_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in

Figure 7-92 and described in Table 7-64.

Return to the Register Summary Table.

SerDes Lane n Status (n = 0 - 15). LANE_STATUS[0] is at the lowest address.

Note

Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-92. LANE_STATUS[15:0] Register

RESERVED

LANE_STATUS[n]

R-00h

Table 7-64. LANE_STATUS[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

RESERVED

00h

F_EMB_SYNC[n]

Returns 1 if logical lane n has frame or EMB synchronization.

CG_BK_SYNC[n]

Returns 1 if logical lane n has code-group or block synchronization.

SIG_DET[n]

Returns 1 if logical lane n is detecting a data signal (using loss-of-

signal detector in PHY).

7.5.3.32 LANE_ERR[15:0] Register (Offset = 0160h) [reset = 00h]

LANE_ERR[15:0] is a set of 16 registers reporting errors for lane n. LANE_ERR[15:0] is shown in Figure 7-93

and described in Table 7-65.

DDS39RF10, DDS39RFS10

SBASB20 – SEPTEMBER 2024

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