DAC39RFS10 datasheet(97/175 Pages) TI2

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SerDes Lane Inversion

Note

Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-89. LANE_INV Register

LANE_INV[15:8]

R/W-00h

LANE_INV[7:0]

R/W-00h

Table 7-61. LANE_INV Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

LANE_INV

R/W

0000h

Program LANE_INV[n]=1 to invert the bitstream through physical

lane n. Use this if the differential pair is swapped between the

transmitter and receiver.

7.5.3.29 LANE_SEL[15:0] Register (Offset = 0130h) [reset for LANE_SEL[ n ]= n ]

LANE_SEL[15:0] forms a crossbar switch, and is a set of 16 registers for specifying which physical lane is bound

to logical lane n. LANE_SEL[15:0] is shown in Figure 7-90 and described in Table 7-62.

Return to the Register Summary Table.

SerDes Lane Select for Logical Lane n (n = 0 - 15). LANE_SEL[0] is at the lowest address.

Note

Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-90. LANE_SEL[15:0] Register

RESERVED

LANE_SEL[n]

R/W-0h

R/W-n

Table 7-62. LANE_SEL[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

LANE_SEL[n]

R/W

Specify which physical lane (0 to 15) is bound to logical lane n.

To bind physical lane p to logical lane n, program LANE_SEL[n]=p.

For example, to bind logical lane 0 to physical lane 3, program

LANE_SEL[0]=3.

Note: This register should only be changed when JESD_EN=0.

7.5.3.30 LANE_ARR[15:0] Register (Offset = 0140h) [Read only, reset = NA]

LANE_ARR[15:0] is a set of 16 registers for measuring the arrival time of lane n. LANE_ARR[15:0] is shown in

Figure 7-91 and described in Table 7-63.

Return to the Register Summary Table.

SerDes Lane n Arrival Time (n = 0 - 15). LANE_ARR[0] is at the lowest address.

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DDS39RF10, DDS39RFS10

SBASB20 – SEPTEMBER 2024

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