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DAC39RFS10 Scheda tecnica(PDF) 64 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 64 Page - Texas Instruments |
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64 / 175 page ![]() DAC TRANSPORT LAYER SCRAMBLER (Required) SERDES TX PHY 64b/66b LINK LAYER APPLICATION LAYER TRANSPORT LAYER DESCRAMBLER (Required) SERDES RX PHY 64b/66b LINK LAYER Logic Device JESD204C Block DAC Device JESD204C Block ANALOG CHANNEL Figure 7-51. Simplified JESD204C Interface Diagram with 64b/66b Encoding Not all optional features of JESD204C are supported by the device. The list of features that are supported and the features that are not supported is provided in Table 7-15 Table 7-15. Declaration of Supported JESD204C Features LETTER IDENTIFIER FEATURE SUPPORTED BY DEVICE? a 8b/10b link layer Yes b 64b/66b link layer Yes c 64b/80b link layer No d The command channel when using 64b/66b or 64b/80b link layer No e Forward error correction (FEC) when using the 64b/66b or 64b/80b link layer No f CRC3 when using the 64b/66b or 64b/80b link layer No g A physical SYNC pin when using the 8b/10b link layer Yes h Subclass 0 Yes i Subclass 1 Yes j Subclass 2 No k Lane alignment within a single link Yes l Subclass 1 with support for lane alignment on a multipoint link by means of the MULTIREF signal No m SYNC interface timing compatible with JESD204A Yes n SYNC interface timing compatible with JESD204B Yes The various signals used in the JESD204C interface and the associated device pin names are summarized briefly in Table 7-16 for reference. Table 7-16. Summary of JESD204C Signals SIGNAL NAME DEVICE PIN NAMES DESCRIPTION Data 6SRX±, 14SRX± High-speed serialized data after 8b/10b or 64b/66b encoding that is received by the SerDes receivers. DDS39RF10, DDS39RFS10 SBASB20 – SEPTEMBER 2024 www.ti.com 64 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DDS39RF10 DDS39RFS10 |
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