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DAC39RFS10 Scheda tecnica(PDF) 89 Page - Texas Instruments

Il numero della parte DAC39RFS10
Spiegazioni elettronici  DDS39RF10 and DDS39RFS10, 10.24GSPS to 20.48GSPS Dual and Single Channel, Multi-Nyquist Direct Digital Synthesizer (DDS)
PDF  175 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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DAC39RFS10 Scheda tecnica(HTML) 89 Page - Texas Instruments

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Figure 7-74. JCTRL Register (continued)
RESERVED
TI_MODE
SUBCLASS
JENC
RESERVED
SFORMAT
SCR
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-00b
R/W-1b
R/W-1b
Table 7-46. JCTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0b
6
TI_MODE
R/W
0b
0 : JESD204C standard mode (default)
1 : TI Mode - set this when using TI FPGA transmitter IP
5
SUBCLASS
R/W
0b
Specify how the elastic buffer is released:
0 : Subclass 0 operation (default). Release the elastic buffer
immediately once all lanes have starting writing to the buffer.
1 : Subclass 1 operation. Release the elastic buffer on a release
opportunity defined by the LMFC/LEMC and RBD.
4
JENC
R/W
0b
0 : Use 8b/10b link layer
1 : Use 64b/66b link layer
3-2
RESERVED
R/W
0b
1
SFORMAT
R/W
1b
Input sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)
0
SCR
R/W
1b
0 : 8b/10b Scrambler disabled
1 : 8b/10b Scrambler enabled (default)
The 8b/10b scrambler is recommended to improve spurious noise
and make sure that certain sample payloads cannot prevent the
JESD204C receiver from detecting incorrect code-group or lane
alignment. This register has no effect on 64b/66b modes (which are
always scrambled).
7.5.3.14 SHMODE Register (Offset = 0104h) [reset = 00h]
SHMODE is shown in Figure 7-75 and described in Table 7-47.
Return to the Register Summary Table.
JESD204C Sync Word Mode
Figure 7-75. SHMODE Register
7
6
5
4
3
2
1
0
RESERVED
SHMODE
R/W-0b
R/W-00b
Table 7-47. SHMODE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
00h
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DDS39RF10, DDS39RFS10
SBASB20 – SEPTEMBER 2024
Copyright © 2025 Texas Instruments Incorporated
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