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SSM3582ACPZ-R7 Scheda tecnica(PDF) 25 Page - Analog Devices

Il numero della parte SSM3582ACPZ-R7
Spiegazioni elettronici  2×, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier
PDF  58 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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SSM3582ACPZ-R7 Scheda tecnica(HTML) 25 Page - Analog Devices

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Data Sheet
SSM3582A
Rev. A | Page 25 of 58
THEORY OF OPERATION
OVERVIEW
The SSM3582A is a stereo, Class-D audio amplifier with a filterless
modulation scheme that greatly reduces external component
count, conserving board space and reducing system cost. The
SSM3582A does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM) to
generate the output switching pattern, whereas the SSM3582A
uses Σ-Δ modulation, resulting in important benefits. Σ-Δ
modulators do not produce a sharp peak with many harmonics
in the AM broadcast band, as pulse-width modulators often do.
Σ-Δ modulation reduces the amplitude of spectral components at
high frequencies, reducing EMI emission that may otherwise
radiate from speakers and long cable traces. Due to the inherent
spread spectrum nature of Σ-Δ modulation, the need for
oscillator synchronization is eliminated for designs incorporating
multiple SSM3582A amplifiers. The SSM3582A uses less power in
quiescent conditions, which helps conserve the power drawn
from the battery or power supply.
The SSM3582A integrates overcurrent and temperature protection
and a thermal warning with optional programmable automatic
gain reduction.
POWER SUPPLIES
PVDD
PVDD supplies the output power stages, as well as the low
dropout (LDO) regulator for AVDD and DVDD.
AVDD
AVDD is the analog supply used for the modulator, power
stage driver, and other analog blocks.
When the AVDD_EN pin = PVDD, the internal regulator
generates 5 V and the AVDD pin is used for decoupling only.
When the AVDD_EN pin = AGND, 5 V must be provided to
the AVDD pin from an external system source, minimizing
power losses.
DVDD
DVDD supplies the digital circuitry. The current in this node is
very low, below 1 mA.
When the DVDD_EN pin = AVDD, the internal regulator
generates 1.8 V and the DVDD pin is used for decoupling only.
When the DVDD_EN pin = AGND, 1.8 V must be provided to
the DVDD pin from an external system source, minimizing
power losses.
Table 12 summarizes the power dissipation in various supply
configurations, operating modes, and load characteristics.
Table 12. Typical Power Supply Current Consumption for fS = 48 kHz1
AVDD_
EN Pin
Load
Test
Conditions
PVDD
5 V
12 V
16 V
AVDD
Pin
IAVDD
(mA)
IDVDD
(mA)
IPVDD (mA)
Total Power
(mW)
IPVDD (mA)
Total
Power
(mW)
IPVDD(mA)
Total
Power
(mW)
Low
No load
SPWDN = 1
External
0.007542
0.00268
0.000065
0.042859
0.000065
0.043314
0.000065
0.043574
Automatic
power-down
External
0.007542
0.04372
0.000065
0.116731
0.000065
0.117186
0.000065
0.117446
Dither input
External
6.335
0.945
2.54
46.076
4.94
92.656
6.25
133.376
PVDD
No load
SPWDN = 1
Internal
N/A
N/A
0.000065
0.000325
0.000065
0.00078
0.000065
0.00104
Automatic
power-down
Internal
N/A
N/A
0.209
1.045
0.286
3.432
0.329
5.264
Dither input
Internal
N/A
N/A
9.78
48.9
12.38
148.56
14.05
224.8
Low
8 Ω + 33 µH
SPWDN = 1
External
0.007542
0.00268
0.000065
0.042859
0.000065
0.043314
0.000065
0.043574
Automatic
power-down
External
0.007542
0.04372
0.000065
0.116731
0.000065
0.117186
0.000065
0.117446
Dither input
External
6.432
0.942
2.59
46.8056
5.02
94.0956
6.31
134.8156
PVDD
8 Ω + 33 µH
SPWDN = 1
Internal
N/A
N/A
0.000065
0.000325
0.000065
0.00078
0.000065
0.00104
Automatic
power-down
Internal
N/A
N/A
0.209
1.045
0.286
3.432
0.329
5.264
Dither input
Internal
N/A
N/A
9.82
49.1
12.39
148.68
13.73
219.68
1
N/A means not applicable.



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