LAN9312 datasheet(10/458 Pages) SMSC

10 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9312

DATASHEET

14.5.3.14

Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 382

14.5.3.15

Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) ............................................................ 383

14.5.3.16

Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. 384

14.5.3.17

Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) ..................................................................................... 386

14.5.3.18

Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)..................................................................................................... 387

14.5.3.19

Switch Engine Port State Register (SWE_PORT_STATE)........................................................................................................................... 388

14.5.3.20

Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) ................................................................................................................ 389

14.5.3.21

Switch Engine Port Mirroring Register (SWE_PORT_MIRROR).................................................................................................................. 390

14.5.3.22

Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) ................................................................................................... 391

14.5.3.23

Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) .......................................................................................................... 392

14.5.3.24

Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)................................................................................................... 393

14.5.3.25

Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) .................................................................................... 394

14.5.3.26

Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)......................................................................................... 395

14.5.3.26.1Ingress Rate Table Registers ................................................................................................. 396

14.5.3.27

Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) .................................................................... 397

14.5.3.28

Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)............................................................................... 398

14.5.3.29

Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) ............................................................................... 399

14.5.3.30

Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) .................................................................................. 400

14.5.3.31

Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) ..................................................................................... 401

14.5.3.32

Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) ..................................................................................... 402

14.5.3.33

Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) ........................................ 403

14.5.3.34

Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ........................................... 404

14.5.3.35

Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) ........................................... 405

14.5.3.36

Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) ............................................................................... 406

14.5.3.37

Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) .................................................................................. 407

14.5.3.38

Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) .................................................................................. 408

14.5.3.39

Switch Engine Interrupt Mask Register (SWE_IMR)..................................................................................................................................... 409

14.5.3.40

Switch Engine Interrupt Pending Register (SWE_IPR)................................................................................................................................. 410

14.5.4 Buffer Manager CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

14.5.4.1

Buffer Manager Configuration Register (BM_CFG) ...................................................................................................................................... 412

14.5.4.2

Buffer Manager Drop Level Register (BM_DROP_LVL)............................................................................................................................... 413

14.5.4.3

Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)............................................................................................... 414

14.5.4.4

Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) ........................................................................................ 415

14.5.4.5

Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)............................................................................................................. 416

14.5.4.6

Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) .................................................................................................... 417

14.5.4.7

Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) ....................................................................................................... 418

14.5.4.8

Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) ....................................................................................................... 419

14.5.4.9

Buffer Manager Reset Status Register (BM_RST_STS) .............................................................................................................................. 420

14.5.4.10

Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD) ................................................................ 421

14.5.4.11

Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) ........................................................... 422

14.5.4.12

Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)............................................................ 423

14.5.4.13

Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) ................................................................................................... 424

14.5.4.14

Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) .................................................................. 426

14.5.4.15

Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03) .................................................................. 427

14.5.4.16

Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) .................................................................. 428

14.5.4.17

Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13) .................................................................. 429

14.5.4.18

Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) .................................................................. 430

14.5.4.19

Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23) .................................................................. 431

14.5.4.20

Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) .......................................................................................... 432

14.5.4.21

Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) ............................................................................................. 433

14.5.4.22

Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) ............................................................................................. 434

14.5.4.23

Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII) ................................................................... 435

14.5.4.24

Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) ...................................................................... 436

14.5.4.25

Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) ...................................................................... 437

14.5.4.26

Buffer Manager Interrupt Mask Register (BM_IMR) ..................................................................................................................................... 438

14.5.4.27

Buffer Manager Interrupt Pending Register (BM_IPR) ................................................................................................................................. 439

Chapter 15 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

15.1

Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

15.2

Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

15.3

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

15.4

DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

15.5

AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

15.5.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

15.5.2 Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

15.5.3 Power-On Configuration Strap Valid Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

15.5.4 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

15.5.5 PIO Burst Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

15.5.6 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

15.5.8 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

15.5.9 TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

15.5.10 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

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